As integration density of semiconductor devices including metal oxide semiconductor (MOS) transistors increases, the sizes of the MOS transistors, e.g., channel lengths are gradually being decreased. The respective MOS transistors include a gate dielectric and gate electrode which are sequentially stacked on a channel region between source and drain regions as well as the source and drain regions formed in a semiconductor substrate. The source and drain regions are formed to have shallow junction depths and lightly doped drain (LDD) structures in order to suppress a short-channel effect. In this case, there may be a limitation in decreasing the electrical resistances of the source/drain regions.
Recently, highly integrated semiconductor devices are being designed to use power supply voltage lower than 2 or 3 volts. Therefore, the MOS transistors may suffer from high electrical resistances of the source/drain regions rather than a hot carrier effect and/or low drain breakdown voltage. That is, when the MOS transistors include the source/drain regions having typical LDD structures and shallow junction depths, current drivability of the MOS transistors may be significantly reduced due to the high resistances of the source/drain regions.
In general, after implanting impurity ions into the semiconductor substrate, the source/drain regions may be formed by activating and diffusing the impurity ions at a high temperature of about 800° C. or more. In this case, if the impurity ions are activated and diffused by sufficiently heat treating the substrate having the impurity ions at high temperatures, lateral diffusion lengths of the impurity ions may also be increased as well as vertical diffusion lengths. Therefore, it may be difficult to suppress the short-channel effect because channel lengths between the source and drain regions decrease. On the contrary, if the heat treatment time and temperature are not sufficient to activate the impurity ions, the decreasing of the channel lengths can be prevented. However, crystal defects, such as dislocations generated in the semiconductor substrate during the ion implantation process, may not be cured due to the insufficient heat treatment. These crystal defects may cause an increase in junction leakage current of the source/drain regions.
As described above, it may be difficult for the ion implantation process to form source/drain regions appropriate for highly integrated semiconductor devices. In addition, even if the source/drain regions are formed using the ion implantation process, there may be a limitation in forming the source/drain regions to have abrupt junction profiles. That is, even if sufficiently activated deep source/drain regions are formed using the ion implantation and heat treatment processes, there may be a limitation in decreasing the electrical resistances of the source/drain regions.